1. Field of the Invention
The present invention is related to integrated circuit fabrication. More specifically, the present invention is related to a method and apparatus for identifying assist feature placement problems.
2. Related Art
Semiconductor manufacturing technologies typically include a number of processes which involve complex physical and chemical interactions. Since it is almost impossible to perfectly control these complex physical and chemical interactions, these processes typically have process variations that can cause the characteristics of the actual integrated circuit to be different from the desired characteristics. If this difference is too large, it can lead to manufacturing problems which can reduce the yield and/or reduce the performance of the integrated circuit.
Consequently, to be economically viable, a semiconductor manufacturing process has to be robust with respect to process variations, i.e., it must be able to tolerate a large enough range of process variations. (We describe the present invention in the context of “depth of focus,” which usually refers to process variations in photolithography. But, it will be apparent to one skilled in the art that the present invention can be readily applied to include other manufacturing process variations, such as, dose variation, resist thickness variations, etch variations, and doping variations.)
Note that improving the depth of focus directly results in cost savings. This is because it can substantially increase the throughput by reducing the amount of time spent on inspection, servicing, and maintenance of the equipment. In addition, the actual process conditions encountered during manufacturing may vary due to a variety of reasons. For example, topographical variations on the wafer can occur due to imperfections in the chemical-mechanical polishing process step. As a result, improving the depth of focus can increase the yield for chips that are manufactured in the presence of these process variations.
Depth of focus can be improved by using assist features. Note that assist features can be printing (e.g., super-resolution assist features) or non-printing (e.g., sub-resolution assist features). In either case, assist features are meant to improve the depth of focus of the patterns on the mask layout intended to be printed on the wafer.
Unfortunately, using assist features to improve depth of focus can be very challenging, especially at deep submicron dimensions. Process engineers typically create sophisticated rule tables that specify the shape and placement of assist features from empirical wafer data. Unfortunately, assist feature rule tables can result in missed or sub-optimal placement of assist features. Furthermore, at deep submicron dimensions, assist feature rule tables can be extremely large and unwieldy. Moreover, assist feature rule tables can be overly restrictive which can prevent designers from being able to achieve the best device performance.
Hence, what is needed is a method and an apparatus to identify assist feature placement problems so that they can be corrected, thereby improving the manufacturability of the mask layout.